Computer Engineering Project

Computer engineering is a discipline that integrates several fields of electrical engineering and computer science required to develop computer systems. Computer engineers are involved in many hardware and software aspects of computing, from the design of individual microprocessors, personal computers, and supercomputers, to circuit design. This section is dedicated to computer engineering project ideas, computer engineering projects for students, computer engg project topics, computer engineering project ideas, final year project list, computer engineering project titles.

Retargeting a C Compiler for a DSP Processor

The purpose of this thesis is to retarget a C compiler for a DSP processor. Developing a new compiler from scratch is a major task. Instead, modifying an existing compiler so that it generates code for another target is a common way to develop compilers for new processors.This is called retargeting. This thesis describes how this was done with the LCC C compiler for the Motorola DSP56002 processor. Contents 1 Introduction 1.1 Background 1.2 Purpose and goal 1.3 The reader 1.4 Reading guidelines 2 DSP 2.1 Introduction 2.2 Motorola DSP56002 2.2.1 Data buses 2.2.2 Address buses 2.2.3 Data ALU 2.2.4 Address generation unit 2.2.5 Program control unit 2.3 Instruction set 2.4 Assembly 3 Compilers 3.1 Introduction 3.2 The analysis-synthesis model 3.3 Phases 3.4 Analysis 3.4.1 Lexical analysis 3.4.2 Syntax analysis 3.4.3 Semantic analysis 3.5 Synthesis 3.5.1 Intermediate code generation 3.5.2 Code optimization 3.5.3 Code generation 3.6 Symbol table 3.7 Error handler 3.8 Front and back end 3.9 Environment 3.9.1 Preprocessor 3.9.2 Assembler 3.9.3 Linker and loader 3.10 Compiler tools 4 LCC 4.1 Introduction 4.2 C 4.3 The compiler 4.3.1 Lexical … [Read more...]

Implementation of a Scheduling and Allocation Algorithm for Hardware Evaluation

In this thesis, an intuitive approach to determine scheduling and allocation of a behavioral algorithm defined by a netlist is presented. In this approach, scheduling is based on a weighted list scheduling where operations have the longest critical path are scheduled first. The component allocations are resorted to the PDCPA algorithm which focus on making efficient and correct clusters for hardware reuse problem... Contents 1 Introduction 1.1 Motivation 1.2 Objective 1.3 Related work 1.4 Limitations 1.5 Organization of this thesis 2 Background 2.1 Behavioral synthesis 2.2 MATLAB 2.3 Netlist 2.4 Scheduling 2.5 Allocation 2.6 NP-Complete Problem 2.7 Partition problem 3 Theoretical study 3.1 Behavioral synthesis process 3.2 Scheduling techniques 3.2.1 ASAP (As Soon As Possible) Scheduling 3.2.2 ALAP (As Late As Possible) Scheduling 3.2.3 List Scheduling 3.2.4 Force-Directed Scheduling 3.2.5 Integer Linear Programming algorithm 3.2.6 Classification of scheduling 3.3 Allocation techniques 3.3.1 Greedy allocation 3.3.2 Left Edge (LE) Algorithm 3.3.3 Clique partitioning 3.3.4 Classification of allocation algorithm 4 Description of the program 4.1 … [Read more...]

Speculative Data Distribution in Shared Memory Multiprocessors

This work explores the possibility of using speculation at the directories in a cache coherent non-uniform memory access multiprocessor architecture to improve performance by forwarding data to their destinations before requests are sent. It improves on previous consumer prediction techniques, showing how to construct a predictor that can handle a tradeoff of accuracy and coverage. This dissertation then explores the correct time to perform consumer prediction, and show how a directory protocol... Author: Leventhal, Sean Source: University of Maryland Download This Report Reference URL: Visit Now Reference URL: Visit Now Contents 1 Introduction 1.1 Motivation 1.2 Summary of Work 1.2.1 Consumer Prediction 1.2.2 Migratory Prediction 1.2.3 Timing Prediction 1.2.4 Combined Coherence Prediction 1.3 Research Contributions 2 Background 2.1 Multiprocessor Design 2.2 Memory Sharing Patterns 2.2.1 Migratory Data 2.2.2 Widely Shared Data 2.3 Multiprocessor Memory Coherence 2.4 Coherence Prediction 2.4.1 Inward Coherence Prediction 2.4.2 Outward Coherence Prediction 2.4.3 Administrative Coherence Prediction 2.5 Coverage of Previous Work 2.5.1 Division of … [Read more...]

A Proposed Taxonomy of Software Weapons

The computer security community of today can be compared to the American Wild West once upon a time; no real law and order and a lot of new citizens. The terms and classification schemes used in the computer security field today are not standardised. Thus the field is hard to take in, there is a risk of misunderstandings, and there is a risk that the scientific work is being hampered.Therefore this report presents a proposal for a taxonomy of software based IT weapons. After an account of the theories governing the formation of a taxonomy, and a presentation of the requisites, seven taxonomies from different parts of the computer security field are evaluated. Then the proposed new taxonomy is introduced and the inclusion of each of the 15 categories is motivated and discussed in separate sections... Contents 1 Introduction 1.1 Background 1.2 Purpose 1.3 Questions to be answered 1.4 Scope 1.5 Method 1.6 Intended readers 1.7 Why read the NordSec paper? 1.7.1 Chronology of work 1.7.2 Sequence of writing 1.7.3 Line of thought 1.8 Structure of the thesis 2 The abridged NordSec paper 2.1 A Taxonomy of Software Weapons 2.1.1 A Draft for a Taxonomy 3 Theory 3.1 Why do … [Read more...]

Serial protocol engine for USB 1.1 device

USB has become a popular interface for exchanging data between PC’s and peripherals. An increasing number of portable peripherals are using the USB interface to communicate with the PC. The design and implementation of a synthesizable model of the USB 1.1 protocol engine is presented in this report The PHY is compatible with the USB 1.1 transceiver macrocell interface (UTMI) specification and the simulation test confirmed the successful operation of circuits for both full speed (12 Mbps) and low speed (1.5 Mbps) data transmission. the model is written completely in behavioral verilog with a top down approach and the model was verified and validated. Contents CHAPTER 1 Introduction 1.1 Motivation 1.2 Objective of the Thesis 1.3 Overview of the Task 1.4 Design of the System and Tools Used 1.5 Document Organization CHAPTER 2 LITERATURE OVERVIEW 2.1 Shortcoming of Existing PC IO Paradigm 2.1.1 Cable 2.1.2 Installation and Configuration of Expansion Cards 2.1.3 No Hot Pluggability for Peripherals 2.1.4 Cost 2.2 Analysis of Potential Solution 2.2.1 Access Bus 2.2.2 USB -- The Right Balance 2.3 USB Features 2.3.1 Plug and Play Support 2.3.2 Hot … [Read more...]

Parsing of X.509 certificates in a WAP environment

This master thesis consists of three parts. The first part contains a summary of what is needed to understand a X.509 parser that I have created, a discussion concerning the technical problems I encountered during the programming of this parser and a discussion concerning the final version of the parser. The second part concerns a comparison I made between the X.509 parser I created and a X.509 parser created"automatically"by a compiler. I tested static memory, allocation of memory during runtime and utilization of the CPU for both my parser (MP) and the parser that had a basic structure constructed by a compiler (OAP). I discuss changes in the parsers involved to make the comparison fair to OAP, the results from the tests and when circumstances such as time and non-standard content in the project make one way of constructing a X.509 parser better than the other way. The last part concerns a WTLS parser (a simpler kind of X.509 parser), which I created. Contents 1. Background 1.1. Technical background 1.2. Social background 1.2.1. My situation 1.2.2. The situation at the company 2. The specification of my master thesis 3. The X.509 parser 3.1. General summary 3.1.1. … [Read more...]

Network processor core architecture

This is a master thesis work for SwitchCore AB concerning the design of a network processor for their Gigabit Ethernet switch architecture. Keeping the size down is crucial in order to fit it onto the chip. The result is a small network processor capable of handling Gigabit Ethernet that can be integrated into the architecture. To verify the network processor, a program enabling IPv6 via virtual routing ports was developed. This shows how beneficial a network processor would be when implementing new features. Author: Stenberg, Anders Source: Luleå University of Technology Download Link: Click Here To Download This Project Report (PDF) Reference URL: Visit Now … [Read more...]

Reverse Engineering of Legacy Real-Time Systems

Many real-time systems have significant value in terms of legacy, since large efforts have been spent over many years to ensure their proper functionality. Examples can be found in, e.g., telecom and automation-industries. Maintenance consumes the major part of the budget for these systems. As each system is part of a dynamically changing larger whole, maintenance is required to modify the system to adapt to these changes. However, due to system complexity, engineers cannot be assumed to understand the system in every aspect, making the full range of effects of modifications on the system difficult to predict. Effect prediction would be useful, for instance in early discovery of unsuitable modifications. Accurate models would be useful for such prediction, but are generally non-existent.With the introduction of a method for automated modeling, this thesis applies an industrial perspective to the problem of obtaining models of legacy real-time systems. The method generates a model of the system as it behaved during the executions. The recordings cover system level events such as context switches and communication, and may optionally cover data manipulations on task level, which … [Read more...]

Voice over IP for Sony Ericsson Cellular Phones

This report presents an investigation of the possibilities to implement voice over IP (VoIP) in Sony Ericsson cellular phones. The results from this investigation show that it is partially possible to implement such a solution. The best option for doing so is to make use of the support for the Session Initiation Protocol and the Real-time Transport Protocol offered by the architecture. Another goal is to evaluate if Bluetooth is able to handle the requirements needed for the solution. The whole concept is proven by implementing a prototype. Measurements on this prototype show that Bluetooth will be able to handle the requirements of most IP-based voice communication,i.e., in respect to latency and bandwidth. Download This Report Reference URL 1: Visit Now Author: Petter Theander, Thomas Hultgren Source: Blekinge Institute of Technology Contents 1 Introduction 2 A Need For New Communication Technologies 2.1 Circuit-switched Networks 2.2 Packet-switched Networks 2.3 The Internet 3 The Initial Idea 3.1 Background 3.2 Vision 3.3 The Basic Idea 3.3.1 Making an Outgoing Call 3.3.2 Handling Incoming Calls 3.4 Technical Requirements 3.4.1 The Cellular … [Read more...]

A Novel Compressing Analog-to-Digital Converter

Analog-to-digital converters form the backbone of many real world systems. A compression and expansion (companding) capability is a useful tool to increase the signal-to-noise ratio of many of these applications. Frequently, power-signal systems... Contents 1 Introduction 2 Background 2.1 Analog-to-Digital Converter Characteristics 2.1.1 Quantization Error 2.1.2 Dynamic Range 2.1.3 Signal-to-Noise Ratio (SNR ) 2.1.4 Power Consumption 2.1.5 Propagation Delay 2.2 Appropriate Signals 2.3 Sample ADCs 2.3.1 Non-linear Architectures 2.3.2 Flash Analog-to-Digital Converter 3 A New Compressing Architecture Based on the “Flash” Principle 3.1 Description 3.2 Ideal Converter Characteristics 3.2.1 Transfer Function 3.2.2 Quantization Error (Qe) 3.2.3 Resolution 3.2.4 Signal-to-Noise Ratio (SNR) 3.2.5 Dynamic Range 3.2.6 Optimal Signal 3.2.7 Comparing Compressing and Linear Converters 3.2.8 Varying Parameters 3.2.9 Generating Arbitrary Transfer Functions 3.3 Device Characteristics 3.3.1 Static and Dynamic Power Consumption 3.3.2 Transient Delay 4 Implementation 4.1 Analog Circuit Design 4.1.1 Reference Ladder 4.1.2 Input Buffer 4.1.3 Sample/Hold 4.1.4 … [Read more...]

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